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Tutorial : Full-Custom with Cadence Virtuoso IC 6.15

In this tutorial

A simple inverter is presented in this tutorial. This basic circuit is used to exemplify the basic steps in a full-custom design. The tutorial uses:

  • AMS-C35 (austriamicrosystems) Hit-Kit 3.40 updated till 14-03-2012
  • Cadence Virtuoso (IC) 6.15.121
  • Assura 4.12.020
  • QRC Extractor 10.13.065

The design flow was also tested using other PDKs.

Project Set-Up


Graphical interface

Traditional command-line

Open a shell and run the script that configures the environmental variables needed to run the cadence IC with the AMS foundry. This script should be available through the .tcshrc or .cshrc files, which are executed whenever a shell is opened (TCSH or CSH, respectively). The script is executed by running the following command line:


Then, to create a project called tutorial, we use the following syntax:

  mkprj tutorial

The project just created is now the current project. To start the software with the AMS Hit-Kit, one should execute:

  ams_cds -tech c35b3 -mode virt &

If you are in the room i325 (Microelectronics Students’ Group headquarters) use the following command:

 source /afs/

and select the create new project option.

The command sequence presented above are used to create a new project. Once you have created you can jump to the library creation. Otherwise, when you want to continue an already existing project, the following sequence will be enough to do it:

  ams_cds -tech c35b3 -mode virt

Whenever you run the command selprj, a list of projects will be displayed. You can choose the project you want by its number. The '&' is optional, but you should use it if you want to use the same shell to perform other command line actions.

Once again, if you are in the room i325 (Microelectronics Students’ Group headquarters) the command line is the following:

 source /afs/

and choose the select project option, followed by the project you desire.

Creating a library

The user can create a library (ore more than one when it is needed) to store the schematics, layouts and other cell views. To do so, in the Library Manager window one must choose: File → New → Library.

We will name our library inverter. Then, a technology must be attached to the library just created. In this tutorial we will use the technology AMS-C35 with 3 metal option. Therefore, we must attach TECH_C35B3 as techfile. The following pictures summarize these three steps.

Creating your library Attach a techfile Select technology

Creating a schematic cellview

Now we will create the inverter schematic. In the Library Manager window, you should select the library just created (inverter) . Now, click File → New → Cellview and you will get a window similar to the one shown in the following picture.

New schematic

In this window you should write the name of the cell (which we will call inv). The cellview should be named schematic.

After the name, the schematic must be created. The editor Virtuoso Schematic Editor opens automatically. Some help to ease the schematic editing:

  • to add components, click Create → Instance, or in the icon in the sidebar (the one that looks like a transistor).
  • in the technology AMS-C35, the transistors should be chosen from the library PRIMLIB.
  • the transistors are nmos4 and pmos4 with the cellview symbol.
  • to connect components: Create → wire (narrow).
  • the symbols vdd and gnd are in the library analogLib.
  • input and output pins can be included by Create → pin. It is important to conveniently select the direction of each pin.

Schematic view

In order to change the component properties (e.g. the transistor sizes), you can do it when you are about to include the component (instance). Otherwise, you can change it by Edit → Properties → Objects. This opens a window where the main characteristics can be modified by the user. At the end do not forget to save the design: Check and Save.

Tip: To change a component, you can use the shortcut key q followed by a mouse click in the component you want to modify.

Important: Make sure that the Substrate Contact option is enabled in the transistores properties, it will necessary forward.

Symbol definition

Still in the schematic editor, click Create → Cellview → From Cellview. The cellview is the current one (schematic). The following picture contains the required fields.

Cellview symbol

The pins that you want to show up in the symbol should be indicated next (in and out for the present case).

 Symbol options

The window for graphical edition automatically appears. It contains already a generic shape for the cell symbol. It has the pins previously indicated as input and output. The other parameters of the symbol, namely [@instanceName] and [@partName] are solely used to present a number format for the instance when added in the schematic window. Thus, it are not relevant at least for now.

 Generic symbol

You can now save and proceed with File → Check and Save. Alternatively, if you like, you can still change the symbol to a more suitable representation. To do it, choose Create → Import symbol and from the libraries presented, choose a new symbol drawing. The important is that, independently from the shape, at the end the pins are still well defined (delete the imported pins and move the old ones to the new symbol). Do not forget to Check and Save at the end.

A new symbol for the inverter


Simulation set-up

The simplest form to simulate the inverter is beginning from the schematic view. In the window Virtuoso Schematic Editor you should select Launch → ADE. It opens immediately the simulation interface called Analog Design Environment. You should not close the schematic window where the circuit is drawn.

ADE window

The power supply and the input should be defined. In the ADE window select Setup → Stimuli. The voltage supply is defined in Global Sources. Select 3.3 as DC voltage.

The input signal is defined in the Inputs radio button. You should define a square wave with 3.3V.

Do not forget to Enable and Apply to validate the signals. The configuration should match the figures represented below.

Stimuli global sources Stimuli input sources

Simulation analyses

To configure a simulation type, you should do Analyses → Choose. For the present case, configure a transient simulation (tran) as shown in figure.

Transient for inverter

You can define the outputs visualization previously to the simulation. This way, the plots are automatically displayed once the simulation finishes. To do it, choose Outputs → To Be Plotted → Select On Schematic and, in the schematic window, with the left button of the mouse, select the input node and the output node. Finish the selection with the key ESC.

Another possibility is to select the results after the simulation. You can do this in the ADE window by choosing Results → Direct Plot → Transient Signal, and then in the schematic editor choose the input and output nodes for plotting the voltages. Once again, the selection ends with the key ESC.

ADE simulation

To proceed with the simulation in the ADE, select Simulation → Netlist and Run or simply the green play icon. If the signals have been well defined, and if there are no netlist errors, then the results are automatically displayed.

Simulation results of the inverter


During the layout drawings, the ADE and schematic windows can be closed if you prefer. When you leave the ADE window, you can save the simulation status (Save state) in order to avoid repeating the set-up next time you open the ADE for the same circuit.

To proceed with the layout, go back to the Library Manager window and in your library (inverter) create a new cell with the same name inv, but this time with the cellview layout.

Create the layout cellview

The Virtuoso Layout Suite window opens immediately and contains the technology layers.

Important: Before you start the layout, you should check the grid configuration. In the Virtuoso Layout Suite window, choose Options → Display and edit the fields in Grid Controls, particularly the spaces X and Y Snap. The following figure shows the configuration window with the right values.

Grid configuration

To draw transistors with Virtuoso Layout Suite L Editing we can make use of the parametric cells. These are cells that have already the layout of the transistors, and even other components like resistors or capacitors, depending on the design kit of the foundry. Some guidelines are presented next:

  • You can get nmos4 and pmos4 transistors from PRIMLIB by adding an instance like in the schematic window, but now when you insert it you should choose the layout view.
  • For the present design substrate contact of both transistors should be included (choose it in the parametric cell menu).
  • To draw layers you must select the drw version (drawing) of the layer in the Layers tab and create rectangles with the shortcut key 'r'.
  • To draw the routing between contacts use metal 1.
  • To create contacts you should select Create → Via.
  • You can create rulers to measure distances between components. To do this, select Tools → Create Ruler.

Note: If you are using the Virtuoso Layout Suite XL Editing or above you can import all the components from schematic by select Connectivity → Generate → All From Source.

If you would like to consult the design rules, you should contact your CAD Manager to provide you the foundry documents.

Layout of a simple inverter

Now you must name the nodes to match with the schematic view. This is done with labels. The procedure is explained next:

  • Generally, the labels are created for metal1 layers. In the Layers tab select the layer PIN metal1.
  • Next, in the Virtuoso Layout Suite, select Create → Label. The names chosen must match the names defined in the schematic window: in, out, vdd!, and gnd!.
  • If you feel necessary, change the Height size to about 0.5. During this step, if the label is still not visible in the layout window, press TAB.

Important: Do not forget to select the layer PIN metal1 before you create the label. For instance, in the figure, we have vdd! with metal1. Therefore, we have selected PIN metal1 in the Layers and just after that we have created the label. Note that in the figure, the '+' defines the layer that is associated to the label.


Now you must check if there are any errors in your layout, that is, you have to perform the Design Rule Check (DRC). In this tutorial, the Assura software will be used. Thus, select Assura → Run DRC in the layout editor.

For now, just specific rule validations will be checked. A group of rule validations is commonly known as switches. You can find them in the window Run Assura DRC. To define the switches you should select Set Switches and then with the CTRL key you can select more than one switch. Some key informations about the technology we are using in this tutorial:

  • Until the final stage of the layout of circuit, one can use the switches: no_coverage and no_generated_layers.
  • During the phase that we are more interested in the drawing rules violation, one can use also the switches: no_erc and no_info.
  • All the other DRC parameters must not be changed.

Note: switches are foundry dependent.

If you repeat the DRC and if there is already previous data, select OK to overwrite and Yes to stop seeing the current one. After that, select Yes to display the results.

Finally, the DRC only with the switches no_coverage and no_generated_layers should not give any error!

DRC inverter with minimum DRC switches DRC clear

Note: If there are errors. select AV (meaning All Visible) in the Error Layer Window that will show. This allows you to see all the errors existent. Probably you will have to make a refresh on the layout window: Window → Redraw or Window → Fit All. The colours of the errors match the ones given in the Error Layer Window.


Here we will perform the circuit extraction, that is, all the parasitics resulting the layout of the devices (capacitances, diodes, and other components that can exist due to the interaction between different layers). The layout view will also be compared with the schematic (Layout versus Schematic, or simply LVS)

Without any DRC error, select Assura → Run LVS. In the main form press Set Switches, select the resimulate_extracted option and press OK. This ensures the use of this LVS run for RCX.

In the main form press OK to start LVS.

LVS inverter LVS clear LVS clear

Extraction (QRC)

If there are not LVS errors you can proceed with the extraction by Assura → Run QRC and choose the Extraction tab. For the reference node (Ref Node) write gnd!. Proceed with OK.

QRC inverter QRC clear

To see the results, in the Library Manager window, open the resulting view called av_extracted. You can display the symbols by pressing SHIFT+f.

 Extraction view inverter

If you prefer, you can also display the electrical connections between the extracted elements. You just have to configure the display by doing Options → Display and add Nets or other elements in Display Controls.

Extracted view connections menu Extraction view inverter with connections

Post-layout Simulation

Method 1

For the present case, a quick solution is the following: Open the view av_extracted, then from there open the ADE and load the state that you have saved in the schematic simulation (where the voltage values are already configured and also the outputs to be plotted). Then, run the simulation and voilà!

Method 2

Alternatively, and as a method that generally used to any post-layout for any given cell (particularly for many different cells) the post-layout simulation is performed as follows.

In the Library Manager window create a new view in the library inverter (File → New → Cell View), which will be the schematic view of the inverter testbench.

New test bench schematic inverter

Create a circuit as the one shown in figure. Use the cell inv designed by you (use the symbol view). You can find the other devices in the library analogLib. The square waveform generator is vpulse (between 0 and 3.3V, pulse width 2.5n, period 5n, and equal rise and fall times 100p).

The DC supply is vdc with the value 3.3V. The other components are vdd and gnd, also found in the analogLib. With the DC source as depicted in figure the internal nodes are automatically defined (vdd! and gnd!). The pin out is just used to avoid Warning from the simulator, although the use of a capacitive load would be more appropriated to this design.

Test bench schematic inverter

Do Check and Save and you can close the Schematic view. Now, create a new cellview of the cell inv_testbench choosing the tool Hierarchy-Editor and proceed with proceed with OK.

New config view inverter

It will open the configuration window. Choose Use Template and Spectre. Edit the values to match the following figure and proceed with OK.

Before new configuration inverter New configuration inverter

Open now the view config in the Library Manager. Select the Topcell schematic.

Top cell schematic inverter

In the schematic (note that it is the view config) open the ADE. Configure the simulation. The post-layout simulation results are presented below.

Post layout ADE inverter Post layout results inverter

public/tutorials/fullcustomvirtuosoic6.txt · Last modified: 2012/10/26 21:47 by hcavadas