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CMOS Fabrication Process

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Introduction

Integrated-circuits (ICs or aka chips) are fabricated using wafers. Wafers are like thin circular slices of bread, in this case silicon bread. On each wafer hundreds or thousands of individual chips are fabricated. Technically, each of these individual chips is called die, and each die might represent an IC.

There are several semiconductor industries fabricating ICs. We call them foundries or fabs. Generally, each foundry has several IC processes: e.g. 130nm, 90nm, 65nm, etc. They also organize an annual run schedule (i.e. a fabrication calendar) for the production in each process.

Foundry Process Process type/Option
TSMC 65-nm CMOS Low-Power/General Purpose Logic
TSMC 90-nm CMOS Low-Power/Mixed-Signal/Radio-Frequency
UMC 90-nm CMOS Logic/Mixed-Signal/Radio-Frequency
UMC 130-nm CMOS Mixed-Signal/Radio-Frequency
UMC 180-nm CMOS Mixed-Signal/Radio-Frequency
AMS 180-nm CMOS High-Voltage
AMS 350-nm CMOS Mixed-Signal/Radio-Frequency

In order to lower the costs associated to production, MOSIS (in USA) and EUROPRACTICE (in Europe) assemble small projects to complete a wafer, therefore dividing the costs. This is called Multi-Project Wafer (MPW). Afterwards, they cut the dies and individually isolate the projects submitted for MPW.

It follows now the assembly process. Each die is disposed inside a package cavity. For mass-production the package is generally made of plastic (depending also on the application). For small production or circuits in which the temperature can be significantly high, ceramics is often preferred.

The pads are often defined in the die periphery (it is possible to design in other areas of the circuit but it is less common). The thin wires made of aluminium or gold (preferable) that are soldered to the pad are called bondwires. These wired bond the circuit to the outside. On the other end the bondwires are soldered to the leadframe, which consists on the metallic pins that are visible from outside the package.

Wafer

The typical silicon wafer is bulk. The diameters vary generally between 50 to 300mm. The thickness varies with the diameter due to rigidity of the material. The circuits are built on the top of the wafer. These occupy about 1μm, while the remaining material (in terms of thickness) are in the order of hundreds μm, only used to provide mechanical support.

Epitaxial wafers (Epi) are obtained by applying strong doping levels on the typical bulk wafers. On the surface of that wafer a epitaxial layer is grown, that is, a thin silicon layer made of weak or moderate doping levels. This also reduces the susceptibility of latch-up phenomenon.

SOI wafers (Silicon-on-Insulator) are also based on bulk wafers. It are comprised of a oxide layer called BOX (Buried Oxide), and a very thin Si layer.

Bulk wafer
Fig. 3: Bulk wafer.

SOI wafer
Fig. 5: SOI wafer.

Wafer preparation

The foundries usually do not produce the wafers, they buy them. The wafers are fabricated by specific industries. The base material of the wafer is silicon with great purity level. One of the most famous techniques to form silicon ingot is called Czochralski's method, named after the Polish chemist Jan Czochralski who used this process in 1916.

The process can be simplified as follows. The silicon is first melted through heat. A rotative block (the crystal puller) with a small silicon crystal (the crystal seed) is introduced very slowly into the melted silicon.

The temperature is decreased as soon as the seed touches the silicon surface. Gradually, the silicon attaches the seed. Very slowly one lifts up the rotative block. The crystal continues to grow, forming a cylindrical silicon ingot (or boule as also known).

The silicon ingots are then sliced to obtain the circular wafers. The wafer surface is polished through chemical and mechanical techniques to obtain a high-quality substrate in which the semiconductor devices will be fabricated.

The pure silicon of the wafer is then doped. That is, small impurities are added in a controlled way to define the substrate resistivity. The charge carrier type is also defined within the doping process. Hence, one can have n-type or p-type substrates.

When the material is highly doped the resulting resistivity is very low, thus denominated as p+ or n+ whatever the doping case is. On the contrary, when the material is lightly doped the material is referred as p- or n-.

Silicon Processes Overview

Bulk CMOS

The most basic bulk process is the n-well process (also called n-tub). It has a p-type substrate, and an n-well is needed for PMOS devices. The p-well process is the opposite, it has a n-type substrate, and the NMOS devices require a p-well structure. In the following figures an NMOS structure is shown in the left side of each process figure, while in the right side a PMOS is shown.

Other more advanced processes are the twin-tub (or twin-well) depicted in figures.

SOI

SOI process.
Fig. 11: SOI process.

In the Silicon-on-Insulator process (SOI), instead of the typical silicon substrate, an isolating substrate is used. The isolating substrate is called buried oxide (BOX). On the top of the BOX a silicon layer is deposited. It is the body of the transistor and it is where the channel is formed.

Using SOI processes it is possible to build NMOS and PMOS transistors practically side-by-side. The transistors are isolated from each other. Other advantages over the typical bulk processes (n-well or even twin-tub) include: higher density, latch-up phenomena avoidance, less parasitic capacitances and thus much faster devices.

However, SOI wafers are pretty expensive essentially due to the difficulty of silicon deposition on the top of the BOX. Most popular SOI wafer fabrication methods are Smart-cut, and SIMOX.

There are some examples of very demanding applications that had used SOI, for instance: XBOX 360 (Microsoft), Playstation 3 (Sony), AMD dual e quad core processors in 130nm, 90nm and 65nm.

SOS

SOS process
Fig. 12: SOS process.

Silicon-on-Sapphire (SOS) belongs to the family of SOI processes. A silicon thin-film is epitaxially deposited on the top of a sapphire wafer. The sapphire is mono-crystalline form: an aluminium oxide (Al2 O3 ) or alumina. The main advantage on using SOS is its excellent electrical isolation. It is however difficult to align silicon and sapphire crystalline structures.

It is not easy to produce transistors with reduced dimensions in SOS technology. The great use of this type of process can be found in military and space applications, which are environments typically exposed to great radiation (called rad-hard environments).

Strained Silicon

What is? It consists on the silicon deposition on the substrate surface with inter-atomic spaces wider than its own crystalline structure. The silicon atoms stretch themselves in order to get aligned with other atoms. As a consequence, higher distances between atoms are achievable and the forces that interfere with charge motion is reduced. The electron flow is noticeable improved (70%) with lower power consumption.

One method to form strained-Si is to include a SiGe layer, which is very compatible with Si itself.

There are several forms to apply this concept. Some examples are represented in figures. Intel has used this kind of crystalline deformation in Centrino and Pentium processors (90nm). IBM used strained-Si in 90nm and 130nm processes. They used SOI removing the SiGe layer – Strained Silicon Directly on Insulator (SSDOI). Also, AMD has used strained-Si in 130nm processes, and strained-Si in SOI in the 64bit Athlon.

High-K Processes

During decades the silicon oxide (SiO2) has ruled as dielectric between gate and substrate. SiO2 was chosen because it is a native oxide, which is easily formed through thermal growing. Therefore, it consists on an excellent interface since the atoms are naturally aligned.

With the downscale of transistor dimensions, the oxide capacity had to be increased to better control the drive, that is the channel current control that in other words is exactly the so called field-effect of the MOSFET. :-)

That is why the thickness of the gate has been continually reduced with the downscaling. When thickness below 20 angstrom was achieved (i.e. 2nm) – e.g. has a reference, Intel 65nm has about 12 angstrom – the leakage currents increased through oxide tunnels, thus increasing the power consumption and reducing also the reliability.

This looked like a great bottleneck for downscaling. The alternative found for short-channel processes (like sub-45nm processes) was to replace the native oxide by high-K dielectrics such as hafnium (Hf) based – the dielectric relative constant is usually denoted by K. As an example, Intel 45nm processors have high-K dielectrics, which allow the increase of gate capacitance avoiding losses. However, a metal gate is needed instead of a typical silicon structure. This is due to physical issues related to the interface with the dielectric. Table shows some dielectric (K) values. For instance, one can compare SiO2 and the much higher K value for HfO2.

dielectric K
SiO2 3.9
HfO2 25
HfSiO4 15–18
ZrO2 20–25
ZrSiO4 15
Ta2O5 25

Other Processes

There are other processes that are expected to come in a near future, to replace the actual processes. One device that is already gaining popularity is the FinFET. The channel is built in a SOI substrate, as a thin silicon fin, which also forms the body of the transistor.

FinFET
Fig. 18: FinFET.

New processes will only be a reality when manufacturing can be done at low prices. Another process that has also received increased attention is the dual-gate planar transistor. Its main advantage is that the fabrication process is performed layer by layer. However, the main difficulty found is performing a good gate alignment.

CMOS typical process

Mask 1: N-Well formation

  1. Figure ## : Wafer – p type doping.
  2. Figure ## : Initial Thermal Oxidation - Silicon dioxide (SiO2) growth over the wafer surface at high temperature (900–1200 degrees), either wet (water vapour) or dry (oxygen gas).
  3. Figure ## : Photoresist – Photoresist growth over the oxide surface. It is an organic polymer which properties change with UV light.

Mask 2: Definition of active regions

Mask 3: Polysilicon gate

Mask 4: n+ diffusion

Mask 5: p+ diffusion

Mask 6: Contacts

Mask 7: Metalization 1

Mask 8: Via 1

Mask 8: Via 1

Mask 9: Metalization 2

 
public/tutorials/cmosfabricationprocess.txt · Last modified: 2009/10/18 13:57 by cduarte